1. Field of the Invention
The present invention relates to a reprogrammable nonvolatile semiconductor memory formed of Metal Oxide Semiconductor (MOS) transistors and a reprogramming method thereof.
2. Description of the Related Art
With a conventional reprogrammable nonvolatile semiconductor memory formed of MOS transistors, or an Erasable Programmable Read Only Memory (EPROM), there is provided with a semiconductor substrate whose impurity concentration in the surface area is higher than that of an MOS transistor used for a general purpose so as not to reduce the programming speed or so as to improve the programming efficiency. Thus, the threshold voltage, which is applied to a control gate formed on a floating gate through a insulator film of the MOS transistor, of the EPROM is in the range from 1.5 V to 3.0 V and higher than that of the MOS transistor.
When the conventional EPROM is driven by a generally-used supply voltage of 5 V, there arises no problem. However, when it is driven by a lower supply voltage such as 1.5 V, there arises a problem that the data values stored in the storage cells cannot be read since electric currents do not flow in all the MOS transistors constituting the cells, even if the supply voltage of 1.5 V is directly applied to the control gate.
A conventional EPROM developed to solve the problem is shown in FIG. 1, in which each storage cell is composed of two MOS transistors. Each of the cell includes an MOS transistor 22 for writing whose threshold voltage is higher than the supply voltage 1.5 V and an MOS transistor 21 for reading whose threshold voltage is lower than 1.5 V. The floating gates of the transistors 21 and 22 are composed of a polysilicon film 11a and the control gates thereof are composed of an N-diffusion layer 13a formed on the film 11a through an insulation film. Metal wirings 20a, 20b and 20c are formed on the layer 13a through an insulation film.
The transistors 21 is formed between the wirings 20a and 20b and the transistors 22 is formed between the wirings 20b and 20c.
When data values are written into the storage cells in FIG. 1, a higher voltage than the threshold voltage is supplied between the source region and the control gate of the transistor 22 to form a channel in the semiconductor substrate of the EPROM. When the stored data values are read from the storage cells in FIG. 1, a higher voltage than the threshold voltage is supplied between the source region and the control gate of the transistor 21 to form a channel in the semiconductor substrate. Since the threshold voltage of the transistor 21 is lower than 1.5 V, the stored data value can be read even if the supply voltage is 1.5 V.
Recently, an EPROM shown in FIGS. 2 and 3 has been developed, in which programmed data values are erased simultaneously. With the EPROM, the threshold voltage of each storage cell can be controlled electrically, so that such MOS transistors for writing and reading as described above are not required and each storage cell can be composed of one transistor. The EPROM shown in FIGS. 2 and 3 has a so-called "Diffusion Self Aligned (DSA) structure" (See Kikuchi et al., "DSA-type Non-Volatile memory transistor with self-aligned gate", Jpn. J. Appl. Phys., Vol. 17, 1977, PP49-54).
In FIG. 2 showing a partial section of the EPROM, there are shown only two of many storage cells arranged in a matrix array on the semiconductor substrate, and in FIG. 3, there are shown only four storage cells thereof.
In FIG. 2, in a surface area of a P-silicon substrate 28, an N-diffusion layer 24a as a common drain region is formed, and N-diffusion layers 24b and 25 as a drain region is formed on each side of the diffusion layer 24a. The respective diffusion layers 25 are formed in the vicinity of the respective diffusion layers 24b so as to surround the respective layers 24b.
A P-diffusion layer 26 is formed in the vicinity of the N-drain region 24a so as to surround the region 24a. The N-drain region 24a and P-diffusion region 26 constitute the DSA structure. Impurity concentration of the surface area of the substrate 28 is made higher than the case of not providing the P-diffusion region 26 due to the region 26, so that a high electric field is formed along the channel when a voltage is supplied between the source region 24a and drain region 24b. As a result, the injection efficiency of the hot electrons to a floating gate can be improved and data values can be written to the cells by a lower drain voltage.
On the surface of the substrate 28, two tunnel oxide films 12 are formed between the respective source regions 24b and the drain region 24a, respectively. A floating gate 11 is formed on each of the films 12. Each of the floating gates 11 is insulated from its surroundings by an oxide film 13 and a control gate 14 is formed on the oxide film 13.
Due to the "tunnel phenomenon", the hot electrons generated in the channel are injected through the oxide films 12 to the floating gates 11 and stored therein, and the stored electrons in the gates 11 are removed through the oxide films 12 to the drain region 24a.
An interlayer insulator film 19 covers the surfaces of the control gates 14 and the oxide films 13 and the exposed surface of the substrate 28. A metal wiring layer 20 is formed on the insulator film 19 except a contact hole thereof. The wiring layer 20 is in contact with the surface of the drain region 24a through the contact hole to electrically connected to the region 24a.
The common drain region 24a, the source region 24b, the diffusion region 25, the floating gate 11 and the control gate 14 on the left side in FIG. 2 constitute an MOS transistor Tr11 shown in FIG. 3. The common drain region 24a, the source region 24b, the diffusion region 25, the floating gate 11 and the control gate 14 on the right side in FIG. 2 constitute an MOS transistor Tr13 in FIG. 3. The wiring layer 20 corresponds to a digit line D11 in FIG. 3. The source region 24b on the left side is connected to a source line S11 in FIG. 3 and the source region 24b on the right side is connected to a source line S12 in FIG. 3.
In FIG. 3, the digit line D11 and a digit line D12 are arranged perpendicular to word lines W11 and W12 and the source lines S11 and S12. The word lines W11 and W12 are parallel to the source lines S11 and S12.
The word line W11 is connected to the control gates of the N-channel MOS transistors Tr11 and Tr12, and the word line W12 is connected to the control gates of the N-channel MOS transistors Tr13 and Tr14. The digit line D11 is connected to the drain regions of the transistors Tr11 and Tr13, and the digit line D12 is connected to the drain regions of the transistors Tr12 and Tr14.
The source line S11 is connected to the source region of the transistors Tr11 and Tr12, and the source line S12 is connected to the source regions of the transistors Tr13 and Tr14. The source lines S11 and S12 are connected to each other.
Other N-channel MOS transistors, word lines, digit lines and source lines, which are not shown in FIG. 3, are arranged and connected similarly.
Next, the data erasing and writing operations of the conventional EPROM shown in FIGS. 2 and 3 will be described below.
When the stored data value in the EPROM are erased, a positive voltage is applied to the source regions of all the transistors including the transistors Tr11, Tr12, Tr13 and Tr14 through all the source lines including the source lines S11 and S12. In each of the transistors, the Fowler-Nordheim current flows between the floating gate and the source region; thus, the electrons stored in the floating gate are drawn out. As a result, the programmed data values stored in all the storage cells are erased simultaneously.
When the data values are stored or the EPROM is reprogrammed, a positive voltage higher than the threshold voltage is applied to the word line connected to the cell or bit to be written, or the control gate thereof, with the source regions of all the transistors through all the source lines being grounded. In the transistors of the cell to be written, an electric current flows along the channel and at the same time, the hot electrons are generated in the channel near the drain region; thus, the hot electrons are injected and stored in the floating gate. As a result, the selected cell is reprogrammed.
With the conventional EPROM in FIGS. 2 and 3, since the impurity concentration in the surface area of the substrate 28 is high, a high electric field can be generated in the surface area along the channel. As a result, there is an advantage that the injection efficiency of the hot electrons can be improved to reprogram the EPROM by a lower drain voltage.
However, the EPROMs described above have the following problems.
With the EPROM shown in FIG. 1, since two transistors are used in one cell or bit, the cell area becomes large, and an additional process such as an ion-implantation is required to reduce the threshold voltage of the transistor for reading in the fabrication process thereof.
With the EPROM shown in FIGS. 2 and 3, dispersion of the threshold voltage of the transistors is generated after the data values are erased.
For example, in case that the data values stored in the transistors Tr11, Tr12, Tr13 and Tr14 shown in FIG. 3 are erased, since the source regions of the transistors Tr11, Tr12, Tr13 and Tr14 are connected each other through the source lines S11 and S12, if the desired threshold voltage reduction of the transistor Tr11 is obtained earlier than those of the transistors Tr12, Tr13 and Tr14 due to a voltage applied to the source lines S11 and S12, the erasing operation has to be stopped even if the threshold voltage reductions thus obtained of the transistors Tr12, Tr13 and Tr14 are not enough for data erasing,
It is the reason that if the erasing operation is continued until the data values stored in all the transistors Tr11, Tr12, Tr13 and Tr14 are erased, the threshold voltage of the transistor Tr11 whose data values are already erased is overreduced and the transistor Tr11 becomes to have a function of a depletion-type one and as a result, a desired potential cannot be applied to the source regions of the transistors Tr12, Tr13 and Tr14 since an electric current flows through the transistor Tr11 even if a potential is applied to the source lines.
On the other hand, if the erasing operation is stopped when the data values stored in the transistor Tr11 are erased, the threshold voltages of the transistors Tr12, Tr13 and Tr14 become higher than that of the transistor Tr11.
There has not been developed any technique which can erase the data values stored in all the storage cells simultaneously without the threshold voltage dispersion and can put it to a practice use in EPROMs such as one in FIGS. 2 and 3.
It is possible to erase the stored data value per cell instead of erasing the data values in all the cells simultaneously. However, wirings are required to be formed so as to connect the respective cells, or the respective sources of the transistors, separately, and as a result, the cell area increases sharply.